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ssss1 Scanning electron microscopy (SEM) image of the cross‐section of a 3D IC test device. It has only two pieces of Si chips stacking on a polymer board.

In the interposer, there are arrays of vertical through‐Si‐vias (TSV) plated with Cu, making connections to the third arrays of solder joints of diameter about 10–20 μm, the so‐called micro‐bumps or μ‐bumps, which join the interposer to the top Si chip. The top Si chip is an active device chip, so it has transistors. The thickness of the device in ssss1 is about that of a US penny. The thinness of the device is a critical requirement due to the limit of form factor of mobile consumer electronic products. Consequently, the thickness of Si chips is thin too. The thickness of the Si interposer is about 50 μm, which is much thinner than that of a convention Si chip of 200 μm in thickness. The thin interposer has caused the warpage problem, as well as the heat conduction issue, to be discussed in the later chapters. The diameter of the TSV in the interposer is about 5 μm, so the aspect ratio of the TSV is 10.