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Digital VLSI Design and Simulation with Verilog
Dr. Suman Lata Tripathi
Lovely Professional University, Phagwara, Punjab, India
Dr. Sobhit Saxena
Lovely Professional University, Phagwara, Punjab, India
Dr. Sanjeet Kumar Sinha
Lovely Professional University, Phagwara, Punjab, India
Dr. Govind Singh Patel
IIMT College of Engineering, Greater Noida, UP, India
This edition first published 2022
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