Читать книгу Digital VLSI Design and Simulation with Verilog онлайн
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Set in 9.5/12.5 STIXTwoText by Integra Software Services Pvt. Ltd, Pondicherry, India
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6 ssss11.1 Logic Gates1.1.1 Universal Gate Operation1.1.2 Combinational Logic Circuits1.2 Combinational Logic Circuits Using MSI1.2.1 Adders1.2.2 Multiplexers1.2.3 De-multiplexer1.2.4 Decoders1.2.5 Multiplier1.2.6 Comparators1.2.7 Code Converters1.2.8 Decimal to BCD EncoderReview QuestionsMultiple Choice Questionsssss1
7 ssss12.1 Flip-flops (F/F)2.1.1 S-R F/F2.1.2 D F/F2.1.3 J-K F/F2.1.4 T F/F2.1.5 F/F Excitation Table2.1.6 F/F Characteristic Table2.2 Registers2.2.1 Serial I/P and Serial O/P (SISO)2.2.2 Serial Input and Parallel Output (SIPO)2.2.3 Parallel Input and Parallel Output (PIPO)2.2.4 Parallel Input and Serial Output (PISO)2.3 Counters2.3.1 Synchronous Counter2.3.2 Asynchronous Counter2.3.3 Design of a 3-Bit Synchronous Up-counter2.3.4 Ring Counter2.3.5 Johnson Counter2.4 Finite State Machine (FSM)2.4.1 Mealy and Moore Machine2.4.2 Pattern or Sequence DetectorReview QuestionsMultiple Choice Questionsssss1