Читать книгу Digital VLSI Design and Simulation with Verilog онлайн

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13 ssss18.1 Delay Modeling and Programming8.1.1 Delay Modeling8.1.2 Distributed-Delay Model8.1.3 Lumped-Delay Model8.1.4 Pin-to-Pin-Delay Model8.2 User-Defined Primitive (UDP)8.2.1 Combinational UDPs8.2.2 Sequential UDPs8.2.3 Shorthands in UDP8.3 Task and Function8.3.1 Difference between Task and Function8.3.2 Syntax of Task and Function Declaration8.3.3 Invoking Task and Function8.3.4 Examples of Task Declaration and Invocation8.3.5 Examples of Function Declaration and InvocationReview QuestionsMultiple Choice Questionsssss1

14 ssss19.1 Logic Synthesis9.1.1 Technology Mapping9.1.2 Technology Libraries9.2 Introduction of a Programmable Logic Device9.2.1 PROM, PAL and PLA9.2.2 SPLD and CPLD9.3 Field-Programmable Gate Array9.3.1 FPGA Architecture9.4 Shannon’s Expansion and Look-up Table9.4.1 2-Input LUT9.4.2 3-Input LUT9.5 FPGA Families9.6 Programming with FPGA9.6.1 Introduction to Xilinx Vivado Design Suite for FPGA-Based Implementations9.7 ASIC and Its ApplicationsReview QuestionsMultiple Choice Questionsssss1