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4 Chapter 4Figure 4.1 Logic circuit.Figure 4.2 Logic circuit.Figure 4.3 Block diagram of a half adder.Figure 4.4 Logic circuit of half adder.Figure 4.5 Logic circuit of half adder using a NAND gate.Figure 4.6 Logic circuit of half adder using NOR gate.Figure 4.7 Block diagram of a full adder.Figure 4.8 Logic circuit of a full adder.Figure 4.9 Block diagram of a half subtractor.Figure 4.10 Logic circuit of a full subtractor.Figure 4.11 Logic circuit of a half subtractor using a NAND gate.Figure 4.12 Logic circuit of the half subtractor using a NOR gate.Figure 4.13 Block diagram of a full subtractor.Figure 4.14 Logic circuit of a full subtractor.Figure 4.15 Block diagram of a 2 × 1 multiplexer.Figure 4.16 Logic circuit of a 2 × 1 multiplexer.Figure 4.17 Block diagram of a 4 × 1 multiplexer.Figure 4.18 Logic circuit of a 4 × 1 multiplexer.Figure 4.19 Block diagram of 1 × 2 de-multiplexer.Figure 4.20 Logic circuit of a 1 × 2 de-multiplexer.Figure 4.21 Block diagram of 2-to-4 decoder.Figure 4.22 Logic circuit of a 2-to-4 decoder.Figure 4.23 Block diagram of 4-to-2 encoder.Figure 4.24 Logic circuit of 4-to-2 encoder.Figure 4.25 Logic circuit of a 1-bit magnitude comparator.