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2 Chapter 2Figure 2.1 Clocked S-R F/F.Figure 2.2 Clocked D-F/F.Figure 2.3 Clocked J-K F/F.Figure 2.4 Master-slave of a J-K F/F.Figure 2.5 Clocked T-F/F.Figure 2.6 Excitation table of a) S-R, b) D, c) J-K and d) D- F/F.Figure 2.7 Characteristic table a) D-F/F and b) T-F/F.Figure 2.8 SISO shift register block diagram.Figure 2.9 SIPO shift register block diagram.Figure 2.10 PIPO shift register block diagram.Figure 2.11 PISO shift register block diagram.Figure 2.12 3-bit Synchronous up-counter with J-K F/F.Figure 2.13 3-bit ripple counter (up-counter).Figure 2.14 State diagram of a 3-bit up-counter.Figure 2.15 3-bit up-counter logic block.Figure 2.16 4-bit ring counter using D-F/F.Figure 2.17 4-bit Johnson counter using D-F/F.Figure 2.18 Mealy machine.Figure 2.19 Moore machine.Figure 2.20 Design 011 sequence using a Mealy machine.Figure 2.21 State-diagram representation of Moore model.Figure 2.22 Sequence circuit of 011 Mealy sequences.

3 Chapter 3Figure 3.1 Top-down design methodology.Figure 3.2 Bottom-up design methodology.Figure 3.3 Design flow chart.