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5 Chapter 5Figure 5.1 Block diagram of 2 × 1 multiplexer.Figure 5.2 Block diagram of 4 × 1 multiplexer.

6 Chapter 6Figure 6.1 Logic circuit of a full adder [1].Figure 6.2 Block diagram of a 4-bit full adder [1].Figure 6.3 Logic circuit of 4 × 1 multiplexer.Figure 6.4 Block diagram of a 2-to-4 decoder.Figure 6.5 Block diagram of a 4-to-2 decoder.Figure 6.6 Block diagram of the D-Latch.Figure 6.7 Block diagram of a D-F/F.Figure 6.8 Block diagram of the J-K F/F.Figure 6.9 Block diagram of the D-F/F using J-K F/F.Figure 6.10 Block diagram of the J-K F/F using T-F/F.Figure 6.11 Block diagram of an S-R F/F using J-K F/F.

7 Chapter 7Figure 7.1 CMOS design with pull-up and pull-down network.Figure 7.3 MOS switches (a) NMOS (b) PMOS.Figure 7.4 Symbol of a CMOS switch.Figure 7.5 Resistive Switches (a) tran (b) tranif1 (c) tranif0.Figure 7.2 CMOS inverter.Figure 7.6 NAND gate implantation at transistor level.Figure 7.7 AND gate using MOS switches.Figure 7.8 NOR gate using switches.Figure 7.9 OR gate using switches.Figure 7.10 XOR gate using switch.Figure 7.11 2 × 1 Multiplexer block.Figure 7.12 2 × 1 Multiplexer using a CMOS switch.Figure 7.13 4 × 1-multiplexer block.Figure 7.14 4 × 1-multiplexer using switches.Figure 7.15 1-bit full-adder implementation using a 4 × 1 multiplexer.