Читать книгу Digital VLSI Design and Simulation with Verilog онлайн

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11 Chapter 1ssss1ssss1ssss1ssss1ssss1ssss1ssss1ssss1ssss1ssss1Table 1.11 Truth table of the Table 1.12 Truth table of a 1 × 4 de-multiplexer.Table 1.13 Truth table of decoder 2 × 4.Table 1.14 Truth table of a 2-bit comparator.Table 1.15 Octal to Binary converter.Table 1.16 Truth table of a decimal to BCD encoder.

12 Chapter 2Table 2.1 Truth table of an S-R F/F.Table 2.2 Truth table of a D-F/F.Table 2.3 Truth table of a J-K F/F.Table 2.4 Truth table of a T-F/F.Table 2.5 State diagram of a 3-bit counter.Table 2.6 Excitation table of a T-F/F.Table 2.7 State table of a 3-bit counter.Table 2.8 D-F/F excitation table.Table 2.9 State table 1 of sequence 011.Table 2.10 State table 2 of sequence 011.

13 Chapter 4Table 4.1 Half adder.Table 4.2 Full adder.Table 4.3 Half subtractor.Table 4.4 Full subtractor.Table 4.5 2 × 1 multiplexer.Table 4.6 4 × 1 multiplexer.Table 4.7 1 × 2 de-multiplexer.Table 4.8 2-to-4 decoderTable 4.9 4-to-2 encoder.Table 4.10 1-bit magnitude comparator.

14 Chapter 5Table 5.1 Half adder.Table 5.2 Half subtractor.Table 5.4 4 × 1 multiplexer.Table 5.3 2 × 1 multiplexer.Table 5.5 2 × 1 multiplexer.Table 5.6 4 × 1 multiplexer.Table 5.7 2-to-4 decoder.Table 5.8 1-bit magnitude comparator.