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1 Chapter 1Figure 1.1 Symbol of an AND gate.Figure 1.2 Symbol for an OR gate.Figure 1.3 Symbol for a NOT gate.Figure 1.4 Symbol for a NAND gate.Figure 1.5 Symbol for a NOR gate.Figure 1.6 Symbol for a NAND gate.Figure 1.7 Diagram of a combinational logic circuit.Figure 1.8 Block diagram of a H. adder.Figure 1.9 Circuit diagram of a half adder.Figure 1.10 Block diagram of a full adder.Figure 1.11 Full adder logic block.Figure 1.12 Half subtractor.Figure 1.13 Half subtractor logic block.Figure 1.14 Block diagram of the full subtractor.Figure 1.15 Full subtractor logic block.Figure 1.16 Block diagram of the multiplexer.Figure 1.17 Logic diagram of the multiplexer.Figure 1.18 Implementation of function.Figure 1.19 Block diagram of the de-multiplexer.Figure 1.20 1 × 4 de-multiplexer using logic gates.Figure 1.21 Block diagram of a 2 × 4 decoder.Figure 1.22 Logic diagram of a 2 × 4 decoder.Figure 1.23 Implementation of functions using the decoder.Figure 1.24 Block diagram of a 2-bit binary multiplier.Figure 1.25 Circuit diagram of a 2-bit multiplier.Figure 1.26 2-bit comparator block.