Читать книгу Digital VLSI Design and Simulation with Verilog онлайн

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8 Chapter 8Figure 8.1 A simple combinational circuit indicating distributed delay.Figure 8.2 A simple combinational circuit indicating lumped delay.Figure 8.3 Possible path from individual input to output.

9 Chapter 9Figure 9.1 VLSI design flow at RTL level.Figure 9.2 Example of function implementation with PROM.Figure 9.3 Example of function implementation with PAL.Figure 9.4 Example of function implementation PLA.Figure 9.5 CPLD block diagram.Figure 9.6 PAL-macrocellFigure 9.7 FPGA block diagram.Figure 9.8 2-Input LUT.Figure 9.9 3-Input LUT.Figure 9.10 Digital design flow.

10 Chapter 10Figure 10.1 New project creation on Xilinx ISE simulator.Figure 10.2 New source module creation on Xilinx.Figure 10.3 Xilinx platform for Verilog HDL.Figure 10.4 Behavioral simulation on Xilinx platform.Figure 10.5 4-bit ripple-carry full adder.Figure 10.6 4-bit CLA adder.Figure 10.7 4-bit CSA block diagram.Figure 10.8 Truth table and K-map.Figure 10.9 1.8: 4 × 16 decoder using a 2 × 4 decoder.Figure 10.10 8-bit LFSR.