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6 Chapter 6Figure 6.1 IC design style: full‐custom.Figure 6.2 IC design style: standard cell (row‐based).Figure 6.3 IC design style: field programmable gate array (FPGA).Figure 6.4 VLSI design process and flow.Figure 6.5 Evolution of minimum feature sizes in semiconductor manufacturing...Figure 6.6 Wire bonding in a BGA.Figure 6.7 Flip chip bonding packages.Figure 6.8 The package evolution: from MCM to HI.

7 Chapter 7Figure 7.1 The trend of power density along the process advances.Figure 7.2 (a) Cross section of an n‐type transistor. (b) Basic DRAM cell.Figure 7.3 An n‐type transistor with channel length (L) and width (W) [3].Figure 7.4 DRAM cell and block configurations [4]. (a) Schematic circuit for...Figure 7.5 A typical 6T Static RAM cell.Figure 7.6 Illustration of the performance/timing analysis in digital design...Figure 7.7 Illustration of energy‐delay product (EDP) for the trade‐off.Figure 7.8 A power network illustration.Figure 7.9 A clock mesh/tree hybrid architecture for clock network.Figure 7.10 An example of DVFS architecture chip.Figure 7.11 Illustration of MSV designs.Figure 7.12 In MSV designs, level shifters are needed for the signal traveli...Figure 7.13 (a) Temperature distribution of a testcase using the thermal mod...