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8 Chapter 8Figure 8.1 Packaging hierarchy in interposer‐based 3D IC. CoWoS is one of th...Figure 8.2 An illustration for high bandwidth memory (HBM) with interposer....Figure 8.3 TSV fabrication options in 3D IC integration: via‐first, via‐midd...Figure 8.4 Process flow of DRAM/logic die stacking module in [16]: (a) a thi...Figure 8.5 Cross‐sectional view of single chip InFO_PoP with TIV (Through‐In...Figure 8.6 3D power delivery model illustration.

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10 Chapter 10Figure 10.1 Schematic diagram depicting atomic diffusion in a face‐centered‐...Figure 10.2 (a) SEM image of a straight Ni silicide line formed between two ...Figure 10.3 (a) Schematic diagram of the cross‐section of an Al short stripe...Figure 10.4 The lower schematic diagram (b), depicting a joint of an Al line...Figure 10.5 (a) Schematic diagram of an in situ TEM samples, where the elect...Figure 10.6 (a) Schematic diagram depicts a Cu interconnect conductor with a...Figure 10.7 (a) The schematic diagram on the left side depicts a conductor w...Figure 10.8 The upper row of SEM images shows a daisy chain of flip‐chip sol...