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In the above example, besides the active Si chip, the rest, which includes the interposer, can be regarded as electronic packaging. The packaging enables the Si chip to function, as well as to allow us, to interact with the outside world. In the packaging, it is worth mentioning that between two sets of solder joints of different sizes, there should be a redistribution layer (RDL) structure for circuit fan‐out. It increases the number of input–output (I/O) contacts of a circuit in going from a low density of solder joints to a high density of solder joints. The higher the density of I/O, the better the resolution of frequency of a digital electromagnetic wave, because each I/O is designed to transmit a small width of the wave.

At the moment, there are two critically important challenges in electronic packaging technology. The first is the need of denser and denser I/O, which means the diameter of micro‐bump and the pitch between them has to be reduced. As to be shown in ssss1, hybrid‐bonds consist of Cu‐to‐Cu bonds together with dielectric‐to‐dielectric bonds are being developed. The second is Joule heating and heat dissipation, which will be discussed in ssss1.